puestos en TCL en Francia

The goal of the SCE (Secure Connected Edge) team within NXP is to become the leader in its market by leveraging its unique portfolio of IP from NFC and Secure Elements, NFC and UHF tags, Wi-Fi, UWB and Bluetooth products to deliver solutions that are better than the sum of its parts.

NXP is a world leader in security, especially for mobile payment applications and continues to drive growth through innovation.

Working in a fast-paced mobile environment, we are looking for an outstanding System Digital Design Engineer to join our global System Team. This team defines cutting-edge RF/analog systems in the area of PMU, mixed-signal (PLL, ADC, DAC) & radio transceivers (RX, TX). Designing chips in advanced process nodes (40nm, 28HPC, 22FDX, …), our architectures leverage extensively on high-speed & high-performance digital islands, embedded in our RF/analog macros. These islands are in essence either controllers, calibration engines, DSP functions, or critical pieces of the signal paths of our transceivers.

We have an opening for a talented System Digital Design Engineer to take charge of the definition and design of our Digital Islands.

You have excellent communication skills and a proven ability to collaborate across organizational and geographical boundaries. The role might also involve communication with key customers for detailed reviews.

Scope of Responsibilities

As a system digital design engineer in our RF/analog and mixed-signal organization, you will be involved in the entire activity around the definition, design, and verification of our digital islands. You are interested in solving complex analog problems with digital circuits.

In this context, you will work on state-of-the-art highly digitized systems including:

1. DCDC converters (Buck, Boost)
2. PLLs (APLL, DPLL)
3. ADCs & DACs
4. RF receivers & transmitters

Your responsibilities:

• Contribute to the IP architecture definition (PLL, DCDC, ADC, DAC, TX, RX) in strong cooperation with the analog team members.
• Run upfront feasibility studies that conceptually prove the ability to meet speed (MHz to GHz range), power consumption & area targets of critical digital islands. This requires you to quickly compare several digital architectures by running a full digital flow from system definition (Simulink, SystemC) to synthesis & power analysis during this system definition phase.
• Define and design controllers, digital/mixed-signal calibration engines, or dedicated parts of the signal paths (sample rate converters, sigma-delta modulators, decoders, etc.).
• Take ownership of the system model, the RTL design at macro & block level and contribute through various phases of the ASIC/SOC design process, including the full verification (including AMS verification in the context of the full mixed-signal IP/sub-system) & documentation.
• Early run of physical implementation to assess feasibility & area.
• Strongly cooperate with & support the SoC team. Parts of the digital island design (scan, back-end, etc.) might be outsourced to this team.

Your Profile:

• MS or higher in Electrical Engineering or equivalent discipline required.
• 15+ years of relevant experience in Digital Circuit Design. Proficient with Cadence suite.
• Strong analytical and debugging skills.
• Experience in system modeling (MATLAB, Simulink, SystemC, etc.).
• Experience in all aspects of RTL design flow from Specification/Micro-architecture definition to design and verification, Timing Analysis, DFT and physical implementation.
• Proficient in digital design and hands-on experience with Verilog/System Verilog RTL coding.
• Firm understanding and hands-on experience on IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.
• Strong domain knowledge of Clocking, Reset, System modes, Power management.
• Scripting languages (Shell, TCL, PERL, Python).
• Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet).
• Experience with Multiple Power and Clock domains.
• Experience with high-speed (Multi-GHz) digital design.
• Experience with digital design of signal processing functions as: sample rate converters (integer SRC and arbitrary SRC), FIR filters, delta-sigma modulators, clock recoveries, etc.
• Experience with SystemC synthesis tools (Stratus HLS, etc.) would be an asset.
• Good communication and interpersonal skills working in a highly collaborative team.
• Self-Driven with a can-do attitude.