Vaga de Lead Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Lead Software Engineer to work with us in Belo Horizonte, Brazil.

In this role, you will work within Cadence's Verification IPs (VIP) Foundation Technology team, developing and maintaining software libraries written in C and C++, and developing and maintaining a code generation infrastructure written in Java and Perl. Your role will be of a technical lead in the team, supporting peers in writing high-quality, high-performance, architecturally-sound software.

Cadence VIP provides functional verification for SoC (System on Chip) hardware designs. This is a way to accelerate hardware design and verification.

Job Description:

1. Developing and maintaining libraries written in C/C++, which interact with Hardware Description Languages (HDL) such as SystemVerilog. This is essential for ensuring that our software can effectively communicate with each VIP and simulator, which is a fundamental aspect of our product's performance and reliability.
2. Developing and maintaining a code generation infrastructure written in Java and Perl. This infrastructure is crucial for automating the creation of code, which can significantly increase developer productivity, reduce errors, maintain consistency, and accelerate the development cycle.
3. Performing a technical leadership role within the team. This involves guiding the team towards best practices, mentoring junior engineers, and leading by example in terms of code quality and system design.

Requirements:

1. Complete bachelor's in computer science or computer engineering or equivalent experience.
2. 2 to 5 years of experience in software development.
3. Expertise in any of the following: C, C++, Java, Python. If you meet some of these qualifications or have some of these skills, we encourage you to apply.

Nice to have:

1. Good communication skills in English.
2. Scripting experience with any of the following: Python, Perl, Bash.
3. Knowledge of Verilog/SystemVerilog.

Additional Job Details:

Employment category: CLT

Employment term: 40 hours/week. Hybrid work. Competitive benefits.

Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil.