Regional Key Account Manager OTC (all genders)

In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and PD design teams, with a critical impact on delivering best in class PHY designs. You will be required to design best in class PHY.

Description:

Core Responsibilities:

1. Participate in the architecture of next generation DDR PHY.
2. Design DDR PHY from architecture to micro-architecture.
3. RTL implementation of the micro-architecture.
4. Participate in clearly defining specification, testing and verification of the DDR PHY design.
5. Work closely with CAD and PD teams to implement RTL design into GDS.
6. Run various design verification flows at PHY level and provide guidelines to other designers.
7. Participate in establishing CAD and design methodologies for correct by construction designs.
8. Assist in flow development for PHY integration.

Qualifications:

The ideal candidate will have 5+ years of DDR PHY Design experience on high performance, low power SoC designs.

1. Knowledge about industry standards and practices in PHY Design, including RTL writing and verification tools.
2. Experience in developing and implementing DDR PHY.
3. Solid understanding of all aspects of PHY construction, integration, and physical design.
4. Knowledge of basic SoC architecture and HDL languages like Verilog to collaborate with the design team for timing fixes.
5. Knowledge of circuit design and transistor operation is a plus.
6. Power user of industry standard RTL design and synthesis tools.
7. Solid understanding of scripting languages such as Perl/Tcl.
8. Working knowledge of extraction and STA methodology and tools.
9. Good understanding of design methodology to debug issues at PHY level.