Principal Digital Modelling and Design Engineer (f/m/d)

Ready to join the future of innovation in Digital Design Engineering?

This opening is within the Advanced Chip Engineering (ACE) SoC Implementation Organization, a central R&D Design group responsible for end-to-end IC/SoC implementation of the Automotive and Industrial Automation Processors in NXP.

We are seeking a Principal Digital Modelling and Design Engineer (f/m/d) to join our team in Hamburg, Germany. The Hamburg SoC integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment.

International relocation can be accommodated for qualified candidates.

Your Responsibilities:

1. Design, modelling and elaboration of abstractions that enable pre-silicon simulations of HW design using industry CAD tools
2. Creation of HW, IC/IP and SoC models using System C that enable early SW prototyping
3. Programming in Matlab/Simulink: Modelling and abstraction of HW IC/IP from architectural concepts and/or requirements
4. FPGA tooling, design and verification: Creation of HW models from early RTL that enable early development
5. Automation using scripting languages like Python or Perl
6. Analysis, comparison and selection of different circuit topologies for optimal design: Ability to generate models and early RTL using CAD tools
7. Contributing to micro-architecture, RTL design and integration of a System on Chip (SoC) or SoC sub-system, from requirements specification to tape-out and beyond
8. Working with different functions like architecture, verification, DFT, physical implementation, post-silicon validation, etc. to provide early models that enable earlier progress
9. Ability to create models for digital circuits that include the following areas:
1. Digital signal processing IPs: filters, mixers, state machines, etc.
2. Clock and reset infrastructure
3. On-chip interconnect and interfaces
4. ARM CPU/MCU and DSP architectures
5. Design for low power and UPF modelling
6. Communication/control peripherals like PCIe, USB, DDR
7. AMS circuits and IPs including PLLs, receivers, transmitters, LDOs, amplifiers, mixers, etc.
10. Develop and deliver signed-off verilog RTL and associated deliverables (e.g. clock/reset domain constraints, timing constraints, design documentation)
11. Performance, power, area and timing optimizations of your design following requirements and other constraints established by IC SoC Product architects
12. Resolve design problems using knowledge of several of the following areas:
1. Digital signal processing architecture and design
2. Clock and reset infrastructure
3. On-chip interconnect and interfaces
4. ARM CPU/MCU and DSP architectures
5. Design for low power and UPF modelling
6. Communication/control peripherals like PCIe, USB, DDR

Our Team:

As part of the Advanced Chip Engineering R&D team in our company, the product development of a large significant portion of NXP roadmap comes out of this organization and, consequently, there is remarkable visibility to the Corporate NXP Management team.

The candidate would be integrated in a team based in Hamburg, Germany and with day-to-day interactions with other design teams based locally or abroad. Our team has a track record of more than 20 years of successful product designs and innovation.

Your Profile:

1. The candidate should have significant experience with modelling using System C: advanced level is desired
2. Modelling experience using programming in Matlab/Simulink is highly desired
3. Experience with FPGA tooling and design is also a must
4. Proven experience with automation using several programming and scripting languages like Python or Perl
5. Digital IP or SoC design engineer with experience in all aspects of RTL design flow i.e. from specification to micro-architecture, RTL design, verification, timing analysis, area/power estimation and DFT concepts
6. The candidate should have a strong experience in RTL design, digital signal processing, SoC integration, RTL signoff tools (Synthesis/CDC/RDC/Lint)
7. Basic knowledge of compute core (ARM or RISC-V) / DSP architectures as well as ARM-Amba bus protocols would be considered a plus
8. Fluent written and verbal communication in English

Key Soft Skills:

1. Proficient skills in both written and verbal communication, can articulate well
2. Ability to work in a collaborative and fast-paced dynamic environment
3. Can demonstrate emotional intelligence and ability to work well as a part of local and international teams

Education & Seniority:

1. Degree in Electrical Engineering or Computer Science
2. At least 5 years of experience on IP/Sub-system or SoC modelling and digital design