In this role, you will be building the digital part of the SEMRON’s future chip generations. You will design, verify, and optimize digital designs to meet our ambitious performance targets.
What you will do:
Design the digital part of SEMRON’s AI accelerator
Contribute to system architecture exploration efforts
Work closely with analog and software teams to exchange requirements and implement them
Conduct power, performance, and timing analysis
Develop timing constraints
What you should bring in:
In-depth knowledge in RTL design
Experience with RTL simulation tools
A good understanding of digital design trade-offs
Basic knowledge of scripting (e.g. Tcl, Python) and systems programming (e.g. C, C++)