VLSI – Physical Design

As a Physical Design (PD) Engineer, you will be working on PD execution spanning from RTL to GDS with a focus on:

1. Synthesis
2. Floorplan
3. Block P&R
4. Clocking
5. Constraints
6. STA signoff
7. Physical Verification

Tasks include:

1. Implementing RTL to GDS2 flow
2. Handling Floor-plan and Physical Implementation of Power-plan
3. Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, and Physical Verification (DRC & LVS)
4. Crosstalk Analysis, EM/IR, and Formal Equivalence
5. Full Chip Level Floor planning, Bus/Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, and Static Timing Analysis
6. Identifying complex technical problems and summarizing multiple possible solutions
7. Driving and hands-on flow development
8. Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications
9. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
10. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
11. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
12. Familiarity with tools for schematics, layout, and circuit/logic simulation
13. Versatility with scripting to automate design flow (Python/Perl/Tcl/Shell)
14. Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
15. Familiar with Unix/Linux environment
16. Good understanding of computer organization/architecture is preferred
17. Strong analytical/problem-solving skills and attention to detail