Senior Staff / Principal Engineer - Digital Design

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
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This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant’s experience and skills.
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In your new role you will:

1. You will take mixed-signal subsystem design from design implementation to final delivery for chip-level integration.
2. Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements.
3. Ensure all required documentation are prepared according to the quality standards.
4. RTL logic design of modules using Verilog HDL. Designs may include power and clock management units, IP subsystem, high chiplet design, digital interfaces to analog functions, accelerators, filters, etc.
5. Prepare and hold design and verification reviews with technical staff throughout project lifecycle.
6. Perform logic synthesis, timing and power analysis to optimise designs.
7. Pre-silicon verification utilizing various methodologies such as constrained random verification with block/subsystem/chip level UVM testbenches, spice co-simulation of mixed signal blocks and FPGA emulation.
8. Support Validation/bring-up of designs on silicon, providing support to cross-functional teams.

You are best equipped for this task if you have:

1. Bachelor or Master degree in Electrical and Electronic Engineering with minimum 7+ years of professional experience in digital CMOS IC design.
2. Experience using high-level modelling language/tool for designing and evaluating subsystems and algorithms.
3. Strong understanding of digital design, preferably in high speed chiplets design and IP subsystems.
4. Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools, Verilog RTL design.