Senior Staff Analog Layout Engineer

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

We are looking for a Senior Staff Analog Layout Engineer to contribute to the development of High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-speed digital, multi-GHz ADC/DAC, PLL/DLL serial and parallel I/O, and clock generation/distribution for custom ICs). The candidate must have a proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies, successfully performed top-level integrations, and placed products into volume production multiple times.

What You Can Expect

• Own a chip/macro layout.
• Own the overall project schedule, leveraging the design lead and layout manager as needed.
• Work effectively with various groups including layout, design, backend, frontend, ESD, packaging, CAD, etc. Represent layout within the project cross-function team with leading a team, including remote design teams.
• Help implement project specific guidelines and ensure team members follow them.
• Contribute to overall team through tool testing, script development, flow documentation, training, etc.
• Keep abreast of technology and tool developments and bring new ideas to the team.

What We're Looking For

• Bachelor’s or Master's degree in Computer Science, Electrical Engineering or related fields and at least 5+ years of related professional experience.
• Deep understanding of layout methodology from initial chip planning to tape-out.
• Deep understanding of parasitic optimizing in layout.
• Experience in advanced process technology and Fin-FET is preferable.
• High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
• High-level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
• Programming skills in any of the following are a plus: Skill or Ample or Perl, etc.
• Strong technical and analytical background, problem-solving skills, etc.
• Fluent in English.
• Team player.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.