[AI Chip Developer] Back-End IC Engineer (MNC start-up

We are seeking skilled and motivated Back-End IC Engineers to work on cutting-edge chip designs at advanced technology nodes. In this role, you will be responsible for driving the physical design process from RTL to GDSII, with a focus on delivering high-performance, efficient, and robust IC designs. The ideal candidate will be well-versed in layout, integration, and EDA tools, and capable of optimizing and automating design flows.

Key Responsibilities

1. Execute full RTL-to-GDSII back-end flow for SoC design, including floorplanning, partitioning, placement, clock tree synthesis (CTS), routing, and physical verification.
2. Integrate top-down/bottom-up physical design methodologies across advanced technology nodes.
3. Perform static timing analysis (STA), design rule checks (DRC), layout vs. schematic checks (LVS), and engineering change orders (ECO).
4. Collaborate with cross-functional teams to drive design closure and sign-off.
5. Develop or adapt automation flows to enhance productivity and consistency across design phases.

Ideal Requirements

1. Master's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, Physics, Mathematics, or a related field; PhD preferred.
2. Strong understanding of digital back-end design flow and EDA tools.
3. Solid knowledge of timing and physical constraints, and experience in constraint handling for complex SoC designs.
4. Proficient with industry-standard tools such as Genus, Innovus, Quantus, Tempus, Design Compiler, PrimeTime, StarRC, Voltus, and RedHawk.
5. Skilled in scripting (e.g., Tcl, Perl) for tool automation and design flow customization.

If you would like to be considered for this opportunity, please forward a copy of your full CV to melissa.lin@ambition.com.sg