Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Techn[...]

Advance Packaging Integration – Senior Engineer (Package Development Engineering, Silicon Technology Package Integration) (PDE STPI)

We are looking for a Package Silicon Integrator in Package Development Engineering (PDE) Senior Engineer who will lead and drive Micron’s Packaging Technology Development Projects meeting Time to Market (TTM) business unit needs as well as meeting performance targets for Thermal, Electrical, Mechanical, Reliability and Cost. You will collaborate with Micron’s multi-functional team that include Product Development, Wafer level process, Assembly, Test, Manufacturing and Global Quality. Together, we will be responsible for the designing Test Vehicle Development Strategy, and execution to definition, development, and delivery of state-of-the-art product/packages that will shape the future of advanced computing, automotive and mobile products.

Responsibilities will include, but are not limited to:

• Drive package technology integration activities for the silicon test chip development projects and support NPIs to keep roadmap items on track to meet “go to market” timelines.
• Coordinate core team in Development and NPI space of advanced 2.5D/3D packages and standard packaging to drive material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable Design for Manufacturing (DFM) and Design for Reliability (DFR) requirements.
• Evaluate wafer design inclusive of bondpad, scribe, pillars/bump and polyimide, and drive materials and BOM choices such as die thickness and mold compound to meet chip package interaction requirements.
• Drive materials characterization from both package and die components to understand chip package interaction mechanism using TMA, DMA, nanoindentation, and packaging mechanical and thermal stress stimulus.
• Drive novel solutions with silicon design and product teams to recommend the optimum package solutions to meet electrical, mechanical (1st, 2nd, and 3rd level interconnect), thermal, reliability, cost, and other system level requirements.
• Interface closely with multi-functional team that include Product Development, Wafer Level Process, Assembly, Test, Manufacturing and Global Quality and manage the product/package to mass production.

Requirements:

• Bachelor/Masters of Science in physics, materials, mechanical, chemical, or electrical engineering. MS or PhD preferred
• 5+ years of relevant experience in semiconductor manufacturing or a related field, with hands-on experience in semiconductor packaging or Frontend processes, specifically in technology on
• Appreciation for Structured Problem Solving
• Ability to interpret die-, package-, and system-level design and simulation (thermal/mechanical/electrical) methodologies and results
• Knowledge in Chip Package Interaction (CPI)
• Experience and working knowledge with 2.5D/3D heterogeneous integration technologies such as WLFO, SoIC, CoWoS, WoW, InFO, and other chiplet/SiP architectures is a plus
• Experience with wafer bumping, package assembly, substrate technology, BOM selection, testing and product development lifecycle
• Excellent communication skills with the ability to convey complex technical concepts to both technical and non-technical partners
• Demonstrated leadership experience in guiding multi-functional teams and driving technical excellence

Keen on the role? Apply now!