Analog Layout Engineer

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This is an opportunity for an Analog Layout Engineer to join a grow team in the heart of Madrid! The company itself is a telecommunications provider working on solutions for high-speed optical networking.

Key Responsibilities of the analog layout engineer include:

• Layout design of analog and mixed-signal blocks, including ADC, DAC, PLL, TIAs, VCSEL drivers, SerDes, VCOs, and more.
• Schematic-to-layout translation, planning pin positions and defining boundaries.
• Performing physical verification (DRC, LVS) to ensure design integrity.
• Extracting netlists and pre-annotating layout parasitic components for verification.
• Conducting reliability analysis verification, including electromigration and voltage drop.
• Integrating layouts at the system level, ensuring compliance with ESD and latch-up prevention rules.
• Generating LEF files and abstracts for digital co-integration.
• Collaborating with both layout and design engineers for workflow optimization and system alignment.
• Implementing automation scripts to streamline layout processes.
• Researching and adopting new tools to enhance layout efficiency.
  
  

Additional Requirements of the analog layout engineer include:

• An MSc Electrical Engineering, Computer Engineering, or a related field.
• Proven track record in silicon-based design, preferably in high-speed communication systems.
• Expertise in full-custom analog layout techniques in nanometric CMOS technology (65nm/28nm or below).
• Strong proficiency in analog and mixed-signal IC EDA tools such as Cadence or Synopsys.
• Comprehensive understanding of the design flow from schematic to full verification.
• Excellent written and verbal communication skills in English.
• A proactive, analytical, and organized individual who thrives in a collaborative environment.
  
  

If you’re an enthusiastic Analog Layout Engineer and are eager to advance your career, apply today!