Senior Staff IP Validation Engineer

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast-paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

We are seeking a Senior Staff IP Validation Engineer with significant hands-on experience in FPGA IP protocol validation, protocol compliance, FPGA hardware bring-up, and debug.

Requirements

Key Skills

• Hands-on experience in FPGA IP validation with protocol validation equipment is required.
• Experience with detailed IP validation plan creation and execution for IP and Subsystem design validation activities.
• FPGA-based RTL design flows, which include FPGA design entry with Verilog, Timing Closure, Board Bring-up, and Debug with analyzers/scopes.
• Programming skills (e.g., C/C++, Perl, TCL, or Python) for Automated system-level validation.
• Strong background and experience in either Serdes or memory protocols (e.g., PCIe, Ethernet, DDR) and familiarity with associated validation equipment.
• Experience on board development is a plus.
• Experience with standard bus protocols like AMBA AXI, APB, JTAG, UART, I2C/I3C.
• Experience in leading a team on hardware-based validation is a plus.

Education and General:

• BS/MS/PhD in Electronics or Computer Engineering with a minimum of 10-12 years of FPGA or semiconductor Post-Silicon validation experience.
• Strong written and verbal communication skills to work with cross-functional teams.
• Self-motivated and proactive with critical thinking.
• Strong problem-solving and debugging skills.