Senior Library Characterization Engineer

Senior Library Characterization Engineer

Relocation Assistance:
- Relocation allowance – 1 month of salary
- Home passage – return trip tickets for employee, spouse, and kids to home country once a year
- Children international education fee by employer

Work-from-home Policy:
- Hybrid working (1 day WFH per week)

Responsibilities:
• Develop best-in-class library characterization production flow to meet advanced customers’ requirements.
• Responsible for timing and power characterization and generation of standard cell EDA views by implementing and maintaining cell characterization tools and flows for the most advanced silicon modeling methodologies.
• Support the “First Time Right” of IC Designs by ensuring high quality library deliverables. Support liberty model accuracy validation. Develop automatic QA flow including EM/IR and design checks.
• Work closely with the digital library team and support advanced circuit design and modeling, pushing the boundary of what is possible in power, performance, and area.
• Explore innovative modeling techniques for comprehending variation, layout-dependent effects, aging, simultaneous switching, etc.
• Release of digital libraries on our customers' portal following X-FAB standards.
• Work in an international and globally distributed team of experts.
• Customer support for Static Timing Analysis and Signoff condition recommendations.

Minimum Requirements:
• Bachelor’s Degree or higher in Electronics Engineering.
• At least 5 years of experience in digital design activity, specifically at least 2 years in library characterization with spice, internal tools, or commercial tools such as Liberate and static timing analysis with Primetime or Tempus.
• Understanding of digital standard cells, digital circuits & optimization for best-PPA.
• Understanding of Timing/Power characterization & modeling of Standard cell circuits. Knowledge of industry standard hardware design CAD software and required standard cell design view generation and validation.
• Ideally, in-depth understanding of Liberty format (NLDM, CCS, CCSN) and transistor level spice simulation. Hands-on experience running SPICE simulations and high sigma variation analysis.
• Knowledge of static timing, power, EMIR analysis using EDA tools.
• Good layout design knowledge & parasitic optimization in various types of layouts.
• Good communication skills – good level in English, written and spoken.
• Teamwork and collaboration skills, working within a multi-national, multi-site team.
• Open, curious in new design implementation, integrity and friendly when engaging internal/external customers.
• Self-motivated, progressive attitude, and able to work independently with minimum supervision.
• Innovativeness, analytical skills and a structured way of working.
• Good problem-solving skills.

Additional Benefits:
- Career development and training
- Work-life balance
- International secondment program
- Pension provisions
- Bonus schemes
- Health and prevention programs
- Cafeteria and meal subsidy
- Free parking
- Hybrid working (1 day WFH per week)