Verification Engineer

Consol Partners; United Kingdom; On-site; GBP 80,000 - 100,000

Job description

Hi,

This is Abdul from ConSol Partners. One of my clients in Oxfordshire is urgently hiring for a Formal Verification Engineer. This is a fantastic opportunity to dive into a challenging role, offering both personal and professional growth. Please send a copy of your CV if you would like to apply.

Job Description:

Title: Formal Verification Engineer
Location: Oxfordshire, England
Duration: Fulltime, permanent
Work Mode: Onsite

Responsibilities:

1. Mentorship from Principal & Distinguished Engineers.
2. Opportunity to mentor colleagues.
3. Gain insight into various stages of the design & verification cycle.
4. Hands-on experience with leading-edge EDA tools and advanced process nodes, using industry-standard languages and methodologies (e.g., SystemVerilog, UVM, Formal).
5. Work on high-volume data center & enterprise products used by leading industry companies.
6. Plan and manage resource utilization per project.

Requirements:

1. Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or related field.
2. 10+ years of experience in digital ASIC verification, with a strong focus on Formal Verification.
3. Expertise in Formal Verification methodologies, including:
1. Property Checking & Assertion-Based Verification (ABV)
2. Formal Test Planning & Coverage Analysis
3. Formal Sign-Off & Proof Convergence Strategies
4. Hands-on experience with industry-standard formal tools, such as:
1. Cadence JasperGold
2. Synopsys VC Formal
3. Siemens Questa Formal
5. Strong SystemVerilog Assertions (SVA) & PSL (Property Specification Language) knowledge.
6. Ability to translate architecture and design specifications into formal properties and constraints.
7. Familiarity with debugging inconclusive proofs and optimizing proof convergence.
8. Experience in verifying complex protocols (e.g., PCIe, NVMe, DDR, AMBA) using formal methods.
9. Proficiency in scripting for automation (Python, Perl, TCL).