Staff/Principal CPU Design Engineer

Job Description

We are looking for innovative and skilled engineers to join our clients UK team and contribute to the development of modern microprocessors.

As a Principal CPU Design Engineer, you will play a key role in driving innovation, demonstrating technical leadership, and applying in-depth expertise across multiple facets of CPU design.

Responsibilities:

1. Define and create hardware RTL designs optimized for low-power and area efficiency.
2. Write and review technical documentation and specifications for complex designs.
3. Plan, track, and report project progress to ensure high-quality CPU IP delivery within defined timelines.
4. Take ownership of projects across all stages, from concept and specification to implementation, testing, and support.
5. Provide technical leadership and guidance, ensuring the success of the team’s objectives.

Required Skills and Experience:

1. Proficiency with SystemVerilog, Verilog, or VHDL for RTL design.
2. Expertise in synthesizable design, with a strong focus on achieving area, frequency, and power targets while making informed trade-offs between functionality and performance.
3. Proven ability to write detailed specifications and documentation for intricate designs.
4. Demonstrated capability to manage projects end-to-end, covering concept, specification, implementation, and validation.
5. Strong technical leadership and/or team management skills.
6. Practical experience in microprocessor design.

Skills and Experience:

1. Familiarity with SystemVerilog Assertions (SVA).
2. Experience mentoring team members and fostering their growth.
3. Proficiency in scripting such as Python, Perl, or Unix shell scripting.
4. Knowledge of assembly (preferably ARM) and programming such as C/C++.
5. Familiarity with hardware verification, such as SystemVerilog.

This position offers an opportunity to lead the development of cutting-edge microprocessors, contribute to impactful innovations, and guide talented teams within a dynamic, collaborative environment.