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SoC Design Architect (ASIC Digital Systems)

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England

On-site

GBP 65,000 - 85,000

Full time

30+ days ago

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An innovative semiconductor company is seeking a skilled SOC Design Architect to lead the architecture of new chips for exciting products. This role demands a rich background in digital IC design and SOC architecture, with a focus on end-to-end processes from design to tape-out. You'll engage in a dynamic environment, collaborating with a talented team to bring cutting-edge technology to life. If you have a passion for micro-electronics and a desire to work on groundbreaking projects, this is the perfect opportunity for you to make a significant impact in the industry.

5-10 Jahre Erfahrung in digitaler IC-Entwicklung und SOC-Architektur.
Tiefes Verständnis von MCUs, Speicherarchitekturen und SOC-Prozessen.

Verantwortlich für die End-to-End SOC-Architektur neuer Chips.
Zusammenarbeit an brandneuen Produkten auf dem Markt.

Digital IC Design

SOC Architecture

MCUs Subsystems

Memory Controllers

Digital ASIC Flow

RTL Design

SOC Performance Modelling

Low-Power Optimization

Firmware Development

Communication Protocols

BSc in Micro-electronics

MSc in Micro-electronics

PhD in Micro-electronics

Job Description

Working for a cutting-edge semiconductor company, I am looking to recruit a SOC Design Architect for fascinating and brand-new project work.

The position is available for engineers/applicants who can demonstrate experience of full chip design, along with an understanding of architecture and delivery to tape-out.

Salary available is dependent on years of experience - circa £65-85k, with an excellent package and benefits.

Based in Cambridgeshire, you will be tasked with the end-to-end SOC architecture of new chips for brand new products in the market.

Key skills / requirements:

BSc / MSc / PhD in Micro-electronics, physics, or similar field
Approx 5-10 years' experience in digital IC design and SOC architecture
Deep understanding of MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse)
Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST)
Extensive knowledge of SOC architecture, set-up/silicon bring-up, validation and all its associated processes
SOC design, system design, system architecture
IP selection & top-level integration
SOC performance & modelling e.g. UML
SOC interconnect protocols - AXI, AMBA, AHB, APB, OCP, STBus, DTL
DSP / signal processing / communication protocols
Digital-AMS chip development - digital to analog interfaces
Low-power, performance and optimisation
Low level software, firmware and embedded requirements - drivers, controllers etc.

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