SoC/ASIC Design Engineer

zeroRISC

zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they’re built or where they’re deployed.

Role Overview

As a zeroRISC SoC/ASIC Design Engineer, you will design and deliver new high-quality secure silicon at both the top and block level. You will accelerate adoption of zeroRISC products by refining new and existing designs and making the integration process even more seamless. You will interact directly with customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere. We're looking for engineers with strong hardware design skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.

• Design ASICs/SoCs at the chip/top and block level – balancing functionality, performance, power, area, and schedule – throughout the full chip design life cycle from architecture definition to sign-off and post-silicon validation
• Write thorough design specifications
• Author high-quality SystemVerilog following engineering best practices
• Participate with verification team on test plan definition, debug, and coverage closure
• Ensure high-quality full-system design functionality while upholding stringent timelines in collaboration with architecture, verification, physical design, test, software, system, emulation, and silicon validation teams, as well as engineering program managers

• Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
• 4 years of experience with architecture and design of SystemVerilog-based chips and IP blocks
• Experience with design flows including lint, synthesis and timing closure (e.g. SDF)
• Experience with multipower and multiclock domain designs

• Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
• Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)
• Knowledge of computer architecture and memory subsystem architectures
• Experience designing standard components such as ALUs and caches and standard interfaces such as USB and I2C
• Experience with IP block integration
• Experience with UPF and power analysis and estimation
• Experience with CDC and RDC
• Experience with DFD, DFT, and design for verification
• Experience with FPGA and emulation platforms
• Experience with assertion coding
• Experience with scripting languages such as Python

• Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments
• As a seed-stage startup, this role offers significant opportunities for learning and career growth
• Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space