RFIC - PLL Design Engineer

Summary:
Would you like to join Apple’s growing wireless silicon development team? The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple’s state-of-the-art wireless connectivity solutions into hundreds of millions of products.

Key Qualifications:

Description:
As an RFIC-PLL Designer, you are going to be responsible for providing analog and digital PLL solutions for wireless SoC and driving them to mass production for Apple’s Wireless Connectivity products. Responsibilities include:

1. Lead design of radio transceiver chains including analog PLLs - VCOs, digital PLLs - DCOs, LOGen, and chain of blocks in RX, and TX for wireless connectivity products.
2. Drive radio KPI (power, area, performance) to meet product requirements.
3. Work with cross-functional teams including platform architecture, wireless design, RF HW, and SW to define radio features enabling wireless innovation.
4. Work closely with RF Systems in block level and high level specifications of the PLL-LOGen, TX and RX line ups, and proper distribution of spec margins in the chain.
5. Hands-on design contributions starting from concept, architecture and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations and extractions.
6. Design of RF and Analog loopbacks for calibration and compensation.
7. Work through Co-Existence scenarios and design to meet the CoEx requirements.
8. Oversee the floorplan layout and verification of the design to ensure a successful tape-out.
9. Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.
10. Provide design versus silicon measurements correlation and compliance with specification for a volume production.

Work abroad.

Additional Requirements:

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Created on 02/04/2025 by TN United Kingdom