Formal Verification Engineer

Job Description

Formal Verification Engineers – £50k-£130k – Oxford

Due to our continued growth, our semiconductor client is looking for an Formal Verification Engineer to join their cutting-edge SoC team in the development of ASICs. The successful candidates will be working with experts in different aspects of SoC development on state-of-the-art projects.

You will be given the opportunity to undertake role-specific training to further develop your knowledge, experience, and career development.

The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification, and DevOps.

The successful candidate will also be working directly for an industry-renowned Senior Director who has built and established many multi-discipline teams throughout their career, and his teams have enjoyed major success.

This team is going to be a pure multidisciplinary team which can tackle any issue that comes their way and become some of the industry's most well-rounded engineers.

This is a fantastic opportunity for an engineer with 5 to 15+ years of experience in the industry.

Formal Verification Engineers Expected Contributions:

• Mentoring from principal & distinguished engineers.
• Opportunity to become a mentor to your colleagues.
• Understanding of different parts of the design & verification cycle.
• Experience working with leading-edge EDA tools and process nodes using industry-standard methodologies (e.g., SystemVerilog, UVM, Formal).
• Working on high-volume data center & enterprise products used by industry-leading companies.
• Experience of working on projects with teams located internationally.

Formal Verification Essential Qualifications and Skills:

• Graduation with 10+ years of digital ASIC design and verification experience.
• Experience of Formal Verification (Jasper Gold or VC_Formal).
• Practical experience or desire to learn:
• Translating design requirements into RTL.
• Deriving functional requirements for verification.
• SystemVerilog UVM test benches.
• Scripting & REST APIs (e.g., Perl/Python/TCL).
• Team player with good verbal and written communication skills.

Formal Verification Desirable Skills:

• Experience using SV UVM 1800.2.
• Familiarity with C/C++.
• Experience with any of the following storage interfaces: SAS, PCIe, NVMe, or SATA.

Salary and Package:

• Competitive salaries ranging from £50,000 – £130,000 (depending on level and experience).
• 10%-20% bonus (based on company and individual performance).
• 25 days holiday + 8 days bank holiday per year.
• 3 days a week on-site hybrid working.
• Pension (matched group pension up to 8%).
• Life assurance.
• Income protection.
• Private medical.
• Employee supported volunteering.
• Employee assistance program for health well-being, financial services, legal services, etc.
• Training and development.
• Visa sponsorship available.
• Relocation support (if required).

My client can offer a 3-stage process consisting of a 1st stage video call, 2nd stage video call, and a 3rd stage on-site interview (meet the team and site tour). This process can be completed within 2-3 weeks (based on availability).