Senior and Lead Analog PLL Design Engineer - France

Senior and Lead Analog PLL Design Engineer - France

Our client is a fabless semiconductor company specialized in design and marketing of highly integrated, mixed-signal semiconductor products for markets demanding wideband and low power analog-to-digital and digital-to-analog conversion such as Defense & Aerospace, Wired and Wireless Communications, Test & Measurement equipment.

Job function:
Currently seeking a dynamic and experienced analog designer who will contribute to the chip/block level architecture definition and implementation. In this role, the candidate will technically drive analog work-packages to deliver a state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.

Work description:

1. Focus on the architecture and design of high-performance RF PLL.
2. Lead and support analog design work-packages from transistor schematic to GDSII.
3. Participate, in close collaboration with the other project technical leaders, to the definition of the IC architecture and verification methodology.
4. Participate in discussions with customers on product architecture and specification definition.
5. Drive the architecture definition of the analog part(s) under his/her responsibilities.
6. Collaborate with the analog design and layout team to define the specifications of the IC analog sub-blocks for optimal area/power/performance trade-off.
7. Work with the layout team to define the floorplan strategy to meet stringent performance requirements (e.g., speed, matching).
8. Contribute to the design and verification methodology at chip level and sub-blocks level.
9. Define the test strategy of the analog part(s) under his/her responsibilities and drive its implementation.
10. Participate in the evaluation of the fabricated IC in our measurement lab.
11. Work in a team to successfully design a state-of-the-art IC.
12. Animate design reviews.
13. Write documentation in accordance with company Quality Assurance policy.

Qualification and Experience:

1. You have a MSc or PhD in Electrical Engineering or equivalent and several years of hands-on experience in chip-level and circuit-level architecture definition, transistor level design and verification.
2. You have a solid background in low jitter LC based PLL design on integrated circuit for high-speed and high-performance ADC/DAC data converters.
3. You have strong experience in PLL design in advanced node CMOS/FDSOI silicon technologies (22nm and beyond).
4. You have a very good understanding of the entire analog/mixed-signal IC design flow from transistor schematic to GDSII.
5. You have strong experience in mixed-signal IC project and technical leader roles.
6. You have experience in the design of high-speed, low noise and interference robust analog and mixed-signal circuits.
7. You have solid knowledge of analog design and simulation tools (Cadence Spectre).
8. You are creative and proactive.
9. You demonstrate good analytical and problem-solving skills.
10. A strong experience with Cadence design flow is necessary.
11. A strong experience with EM tools is necessary.
12. You are a team player with a critical attitude and sense of initiative.
13. You communicate fluently in English (oral and written).

If you are interested in learning more about this role, get in touch!