Data Scientist Senior HF

Description de poste

We are looking for a Principal Engineer HighSpeed SerDes System Architect to lead nextgen highspeed wireline electrical communication research. Join our HighSpeed HighFrequency team within the Board Engineering Lab at our Grenoble Research Center collaborating closely with HQ technical teams in China to develop 112 Gbit/s SerDes systems.

Location : Grenoble Research Center (Onsite)

Salary : per annum

Employment Type : Permanent

Key Responsibilities

1. HighSpeed Research & Innovation: Lead research in highspeed wireline electrical communications developing new system architectures, designs, models & simulations.
2. NextGen SerDes Development: Explore SerDes PHY architectures (signaling, equalization, FEC) for hyperscale data centers & AI infrastructure.
3. Algorithm Development: Optimize complex parameter spaces through advanced algorithm modeling.
4. Industry Collaboration: Work with universities, research institutions & industry partners participating in IEEE OIF conferences & standards organizations.
5. Technology Roadmap Definition: Develop longterm highspeed interconnect strategies & project planning.
6. Mentorship & Leadership: Supervise interns, PhD students & engineers providing technical guidance.

What You Bring

1. Masters / PhD in Electrical Engineering, Communication Engineering, Information Technology or Signal Processing.
2. 10 years of experience in highspeed wireline electrical communication.
3. Deep expertise in modulation, equalization, synchronization & forward error correction.
4. Proven experience in SerDes architecture (serializer/deserializer) for 56 Gbps, 112 Gbps NRZ & PAM applications.
5. Signal Integrity Expert: Strong background in highspeed link analysis.

Preferred Skills

1. Industry Standards: Knowledge of IEEE 802.3, OIFCEI, InfiniBand, CEI224G.
2. Advanced Signaling: Understanding of highorder modulation (PAM), singleended & bidirectional signaling.
3. SerDes Protocols: Experience with DDR, PCIe and other highspeed interfaces.
4. Hardware Design: Indepth knowledge of SerDes ASICs, DSPs, PCBs, connectors, packaging.
5. Academic & Industry Engagement: Participation in technical conferences & research projects.
6. Innovative Mindset: Passion for technology, problemsolving & highspeed system architecture.

Technical Tools & Work

1. SerDes Modeling & Simulation: Python (preferred), MATLAB, VerilogA, ADS.
2. Signal Integrity Tools: ADS, custom models (MATLAB, Python).

Why Join Us

1. Work on 112 Gbit/s SerDes systems: Cuttingedge technology & highimpact research.
2. Global Collaboration: Partner with top engineers & researchers worldwide.
3. Industry & Research Engagement: Work with leading institutions & participate in global conferences.
4. Shape the Future: Define the roadmap for nextgeneration highspeed communications.

Ready to push the limits of highspeed signal integrity? Apply now!