IC Layout Senior Engineer

Social network you want to login/join with:

Industry: manufacturer of Microprocessors with embedded AI

Location : Remote EU or France (Paris) with occasional travel to Head Office

Markets : Worldwide/International

Cadence tools: Virtuoso and other tools from the Cadence suite

Fine Element analysis tools: Altair SImSolid, Ansys Mechanical, HyperWorks, Femap, ANSYS, Abaqus, Patran, SimScale.

Techniques: Layout automation, Analog layout, analog and mixed-signal circuits, floorplans, block-level layouts, process design rules, ADC Layout, DAC Layout.

Languages: English (mandatory), French is a plus but not mandatory

Your manager: the R&D Director

MISSIONS

As a Layout Engineer within the Analog IC team you will:

1. Lead the layout of custom ICs and analog components while developing automation tools.
2. Design and implement custom layouts for analog and mixed-signal circuits, including custom analog and RF components, while minimizing parasitic effects to enhance the DC and AC precision of analog signals.
3. Create floorplans and block-level layouts for high-performance analog systems.
4. Ensure alignment with process design rules and foundry specifications.
5. Collaborate with foundry engineers to resolve layout-related issues during manufacturing.
6. Develop and utilize custom scripts or tools to efficiently automate repetitive layout tasks.

Profil

1. Extensive experience with the physical layout of ADCs, DACs, and other mixed-signal components.
2. Demonstrated success in completing complex layouts across various node sizes.
3. In-depth expertise in analog layout techniques, including device matching, parasitic minimization, and noise isolation strategies.
4. Proficiency with Cadence tools.
5. Experience in post-layout simulation using FEM tools.
6. Experience with layout automation is a plus.