Digital Verification Engineer

We have had an exciting opportunity become available for a Digital Verification Engineer in France.

ROLE: Digital Verification Engineer
LOCATION: Paris-Caen-Grenoble - France. Remote possible on conditions
DURATION: Permanent

About the company:
Our verification team is looking for a dynamic and highly motivated Digital IC Verification Engineer who will take part in the verification of a state-of-the-art complex and large SoC for the Communications market.
The candidate will be particularly involved in the verification of the digital functions of the ASIC in close collaboration with digital and mixed-signal IC design engineers.

Job Summary:
• Define and implement verification methodologies.
• Elaborate detailed verification plan corresponding to the circuit specifications.
• Write blocks, subsystems, and top-level self-checking test benches, including VIPs.
• Implement regression tests on RTL and gate-level netlists according to the verification plans.
• Support the Analog design team in mixed signal simulations.
• Participate in the evaluation of the manufactured ASIC in our measurement lab.
• Work in a team to successfully verify a state-of-the-art ASIC.
• Write up final test procedures following company QA policy.

Responsibilities:
• Over three years of working experience in RTL verification of digital IC
• Good understanding of digital signal processing and related mathematics
• Specialist with SystemVerilog/VHDL, scripting languages (TCL, Python, Makefile, etc.), and UVM usage, with many years of coding and verification experience
• Team player with a critical attitude and sense of initiative
• Advanced verbal and written communication skills in English
• A previous experience in verification of CPUs (ARM, RISC V) and C-oriented testing is a plus
• A previous experience in the verification of Interfaces such as PCIe, Ethernet, and DRAM is a plus
• A previous experience in verification of digital functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus
• A previous experience with Cadence or Synopsys Simulation flow is a plus
• A previous experience with Cadence or Synopsys Emulators is a plus
• A previous experience in Gate-Level Simulation and/or Formal Verification is a plus

Required experience:
• Master’s Degree or Ph.D. in Electrical Engineering or equivalent

If you could be suitable for this position, please get in touch. See my details below: