Principal Digital Verification Engineer

Job Summary:

A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. MPS products include switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.

Essential Functions:

1. UVM and System Verilog based Digital Verification environment definition and development.
2. VIPs standardization, definition, development and documentation.
3. Define VIP’s integration into the Project’s Digital Verification environment.
4. Digital Verification Metrics definition for RTL and Gate-Level Verification.
5. Test Plan definition and development.
6. Digital Verification Automation and Scripting.
7. Regression’s infrastructure definition, development and management.
8. Close interaction with Senior Digital and Analog Designers to develop VIP models.
9. Lead the Digital Verification Team.
10. Lead and Supervise Digital Verification Tasks of multiple projects.
11. Review Digital Verification Metrics and Results of multiple projects.
12. Define and design Digital Verification Top-Level Tests.
13. Analyze and debug test results, code coverage and functional coverage.
14. Digital Verification estimation, planning and scheduling to meet tape-out dates.

Qualifications:

1. Education: PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
2. Experience: 10+ years of strong experience in ASIC Verification.
3. Experience in power management DC-DC converters + control topologies, such as PWM control, constant–on–time control, and voltage/current mode controls.
4. Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
5. Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
6. Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
7. Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
8. Excellent scripting and automation skills using TCL, Python or C/C++.
9. Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.
10. Good written/verbal communication skills and strong teamwork/collaboration.
11. Knowledge/Experience with the following is a plus:
    1. Automotive standards/FuSA.
    2. I2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN.
    3. Embedded MCU (ARM/RISC V) designs and/or SoC development.
    4. Ability to communicate in Chinese highly desired.

Location:

Barcelona, Spain
Portugal (Lisbon/Porto)
Netherlands (Enschede/Nijmegen)
Switzerland (Tolochenaz)