Principal Digital Design Engineer

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Principal Digital Design Engineer, Barcelona

Client:

Monolithic Power Systems

Location:

Barcelona, Spain

Job Category:

Other

EU work permit required:

Yes

Job Views:

3

Posted:

06.03.2025

Expiry Date:

20.04.2025

Job Description:

Principal Digital Design Engineer

Job Summary:

The candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership to the digital team, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both technical and leadership skills owning and providing technical/schedule oversight of PMICs while working closely with multi-disciplinary groups to drive & design key aspects of ASIC/power management ICs that meet the requirements of products. The candidate will be the lead designer, support verification, and be the technical focus on one or more devices and/or sections. The candidate will also support pre/post-silicon design validation and support Design/ATE/Application & Systems group.

MPS products include switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital cameras, automobiles, and network equipment.

Essential Functions:

• Support & develop the chip/digital level architecture and functional blocks.
• Provide technical documentation with specifications, block diagrams, and requirements to stakeholders.
• Collaborate & work with departments/stakeholders for architectures, requirements, and tradeoffs, including Digital/Analog Design, Application/Test Engineering, & Reliability/Operations to resolve design, application, or test issues.
• Develop system and chip level simulation verification techniques and methodology.
• Digital Design (RTL design): ASIC or FPGA from concept to implementation.
• Digital Verification: Guide development of test plans, test benches, and automated test cases.
• Knowledge and/or responsibility in synthesis, timing closure, and formal verification.
• Create scripting to support design and verification automation.
• Estimate and manage time/tasks completion to target schedule.

Qualifications:

• PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
• 10+ years’ experience in design plus verification of ASIC or FPGA.
• Experience in power management DC-DC converters + control topologies, such as PWM control, constant–on–time control, and voltage/current mode controls.
• Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics.
• Experience with programming, scripting, and automation languages (C/C++, shell, Perl, TCL, Python, etc.).
• Solid knowledge and experience working through the entire ASIC Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
• Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
• Good written/verbal communication skills and strong teamwork/collaboration.
• Experience with automotive standards/FuSAI2C, I3C, SPI, USB, PMBUS, I2S, CAN, LIN Embedded MCU (ARM/RISC V) designs and/or SoC development. Ability to communicate in Chinese is highly desired.