Senior Verification Engineer

Job Description:

Responsibilities:

1. Work closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules.
2. Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure.
3. Develop and execute test and coverage plans to ensure the functional, performance and power completeness.
4. Create, reuse and debug testbenches, verification components and tests for verification of the design.
5. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

Experience And Education:

1. Minimum 5+ years of verification experience on large ASIC development projects.
2. Solid understanding of Computer Architecture and Digital Design concepts.
3. Very strong background in Verilog, System Verilog, C/C++/OOO coding techniques.
4. Experience working with UVM, OVM or equivalent.
5. Experience with constrained random verification, functional coverage and assertions.
6. Experience with formal verification is an added advantage.
7. Familiarity with one of the scripting languages: perl/tcl/ruby/Bash/python.
8. Experience working with industry standards tools such as Client VCS, VC Formal, DVE, Verdi, GDB or equivalent.
9. Strong analytical skills and attention to detail.
10. Bachelor’s (or preferably Master’s) degree in Computer Engineering, Computer Science, Electrical Engineering or similar.