ASIC RTL Design Engineer

Responsibilities

• Contribute to the microarchitecture and RTL coding of blocks, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
• Develop novel ways to automate generation of complex RTL designs.
• Contribute to design methodology, libraries, and code review.